The present invention relates to a memory device and a programming method thereof, and more particularly, to a non-volatile memory device and a method for performing a copy-back operation thereof.
A memory device is classified into a volatile memory device and a non-volatile memory device according to capability of maintaining stored data without power supplied. The volatile memory device cannot sustain stored data when power is interrupted and typical volatile memory devices are a dynamic random access memory (DRAM) and a synchronous random access memory (SRAM). The non-volatile memory device maintains stored data although power is interrupted and a typical non-volatile memory device is a flash memory.
FIG. 1 is a diagram illustrating a basic structure of a non-volatile memory device according to the related art. In FIG. 1, DSL denotes a drain selection line and SSL indicates a source selection line.
As shown, a cell array of a non-volatile memory device, particularly, a NAND flash memory device, includes a plurality of memory cells MC for storing data, a plurality of word lines WL for selecting and activating memory cells MC, and a plurality of bit lines BL for inputting data to the memory cells MC and outputting data stored in the memory cells MC. The plurality of word lines WL and bit lines BL are arranged in matrix. Here, the plurality of memory cells MC are connected between a source selection transistor SST and a drain selection transistor DST in series. That is, the plurality of memory cells MC form a string structure.
A gate electrode of each memory cell MC is connected to a corresponding word line WL. A set of memory cells MC commonly connected to the same word line WL is referred as a page PG. The page PG may be divided into an even page connected to even bit lines BLe and an odd page connected to odd bit lines BLo. An even bit line BLe and an odd bit line BLo may be connected to one page buffer PB. A plurality of strings connected to each bit line BL are connected to a common source line CSL in parallel, thereby forming a memory block MB.
The NAND flash memory device having the above described structure performs a program operation and a read operation by a unit of a page PG and performs an erase operation by a unit of a memory block MB. The NAND flash memory device also supports a copy-back operation. Hereinafter, a copy-back operation of a NAND flash memory device will be described in detail.
The copy-back operation denotes, for example, an operation of providing data stored in a source page to a target page without externally outputting data. The copy-back operation includes a copy-back read operation for reading data stored in a source page and storing the read data in a page buffer PB and a copy-back program operation for programming the stored data in the page buffer PB into a target page. Due to such a copy-back operation, it may not be necessary for the memory device to perform an operation for outputting data to an external device and an operation for loading data on a page buffer PB from an external device. Therefore, the copy-back operation improves a speed of a memory device. For example, when a predetermined block is determined as a bad block, the copy-back operation can be used to transfer data stored in the predetermined block to a normal block.
Here, the copy-back operation may be performed based on an Incremental Step Pulse Program (ISPP) method. The ISPP method repeatedly applies a pulse type program voltage while increasing the pulse type program voltage by a predetermined level. After completely programming a memory cell, a state of the programmed memory cell transits to a program inhibit state. Thus, a memory cell MC having a fast programming speed can be programmed with a comparative low program voltage. However, a memory cell MC having a slow programming speed requires a comparative high program voltage in order to be programmed.
As described above, the ISPP method increases a program voltage by a predetermined level until a page is completely programmed. The ISPP method also sets a maximum program voltage and programs a next page when the program voltage reaches the maximum program voltage. Therefore, the ISPP method programs the next page after the program voltage reaches the maximum page voltage although a memory cell MC abnormally operates, for example, although a part of columns in a memory cell MC is repaired. Hereinafter, it will be described in detail by comparing a normal program operation and a copy-back operation.
When a memory cell MC is programmed, a latch value of a corresponding page buffer PB is changed from ‘logic low level’ to ‘logic high level’. That is, a program voltage is repeatedly applied while increasing the program voltage by a predetermined level until the latch value changes to ‘logic high level’. Since the latch value does not changes to ‘logic high level’ if a memory cell MC is in a repaired column, a normal program operation sets a latch value of a repaired column to ‘logic high level’ before programming a corresponding page.
Unlike the normal program operation, the copy-back operation does not set a page buffer of a repaired column to ‘logic high level’ because the copy-back operation reads data stored in a source page and programs it in a target page. That is, the copy-back operation sustains a latch value of a repaired column as ‘logic low level’ although a corresponding column is repaired. Therefore, when a maximum program voltage is applied, a page buffer PB ends performing the copy-back operation on a current page PG and starts performing the copy-back operation on the next page PG.
If a page includes a repaired column, a maximum program voltage is unavoidably applied to the corresponding page in the copy-back operation according to the prior art. That is, adjacent memory cells MC are interfered to each other due to an unnecessary applied high program voltage. Such interference deteriorates the memory device characteristics.